Lateral mesh pipeline explorer
Interactive companion to the architecture white paper
1. The fundamental trade
Traditional chips treat a defective node as a die-killing failure. This architecture treats it as a latency event. The instruction diverts laterally to a neighbor, borrows that neighbor's equivalent pipeline stage, then returns diagonally to the origin chain at the next stage down.
2. Tagged addressing
Every instruction carries an origin address prefix identifying its home chain. When diverted, the mesh reads this tag to re-inject after the borrowed stage completes.
3. Mutual exclusion and queuing
Each node processes one instruction at a time. When a borrowed instruction occupies a neighbor, that neighbor's own next instruction queues. Contention resolved by waiting, not arbitration hardware.
4. Verification code reuse
Non-adjacent chains share verification sequences. Code space scales with interaction radius, not chain count.
5. The economic thesis
Trade silicon purity cost for mesh routing overhead. If per-node routing is cheaper than purity investment, the architecture wins.
6. Failure cascade boundary
Graceful degradation under sparse defects. Critical: adjacent chains failing at the same stage. At ±1 shunt, two adjacent failures kill routing. At ±4, you need 9.
7. Shunt range tradeoff
±1 = neighbors only, shortest signal, most realistic. ±4+ = extended reach, more tolerant, longer traces, worse signal integrity, more routing and address complexity.
Where this sits
One abstraction layer deeper than NoC. NoC routes packets between compute clusters. This routes instructions between pipeline stages within a single execution unit.
Crossover economics model
Explore where mesh routing overhead becomes cheaper than purity investment.